Problem: Implement Half Adder in Verilog

Objective

A Half Adder is a basic combinational circuit that performs the addition of two 1-bit binary numbers.
It produces two outputs:

• Sum (S) → XOR of inputs
• Carry (C) → AND of inputs

In this tutorial, you will design a half adder using Verilog and test it with all input combinations.

Explanation

The half adder cannot handle carry-in from previous additions (that’s why it’s called half).
It is the simplest building block for binary addition.

• Sum Equation: S = A ⊕ B
• Carry Equation: C = A · B

Requirements

1. Create a Verilog module named half_adder with:

   • Two inputs: a, b
   • Two outputs: sum, carry

2. Implement the equations:

   • assign sum = a ^ b;
   • assign carry = a & b;

3. Write a testbench module to verify the half adder:

   • Apply all 4 input combinations of a and b (00, 01, 10, 11).
   • Check sum and carry.

Expected Truth Table

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