Update the problem details below.
A Half Adder is the simplest digital circuit that performs binary addition. It takes two 1-bit inputs and produces two outputs:
In this tutorial, we will describe how to design and test a Half Adder using RTL (Register Transfer Level) modeling in Verilog.
The Half Adder works with the following logic equations:
Sum Equation: Sum = A ⊕ B
Carry Equation: Carry = A · B
In RTL style:
always
always @(*)
A testbench is used to apply all input combinations and observe the outputs. It should include:
initial
$finish
iverilog
sum
carry
^
|
Nothing to preview yet. Start typing in the editor...
Enter the expected output as valid JSON format that will be used to verify student submissions.