Implement XOR Gate in Verilog

Objective

Design and verify a simple 2-input XOR gate using Verilog.
The design should be tested using a testbench that applies all possible input combinations.

Requirements

1. Create a Verilog module named xor_gate with:

   • Two inputs: a, b
   • One output: y
   • Function: y = a ^ b

2. Write a testbench module to verify the XOR gate:

   • Apply all 4 input combinations of a and b (00, 01, 10, 11).
   • Observe the output y for correctness.

Nothing to preview yet. Start typing in the editor...