Register Wire Demo

Problem Description

Implement a simple module demonstrating the difference between registers and wires in Verilog.

Module Interface

• Inputs:
  • a: 1-bit input
  • b: 1-bit input
• Outputs:
  • wire_out: Combinational output (wire)
  • reg_out: Sequential output (register)

Expected Behavior

• wire_out should be the combinational AND of a and b
• reg_out should be the registered AND of a and b (updated on clock edge)

For wire_out, use continuous assignment. For reg_out, use an always block with clock.