FSM Toggle

Problem Description

Implement a simple finite state machine that toggles between two states on each clock cycle.

Module Interface

• Inputs:
  • clk: Clock signal
  • reset: Reset signal (active high)
• Output:
  • state: Current state (1-bit)

Expected Behavior

• On reset: state = 0
• On each clock edge: state toggles between 0 and 1

Use an always block triggered by the clock edge. Remember to handle the reset condition.