Problem: Implement Full Adder in Verilog Using gate level modeling

Objective

A Full Adder adds three 1-bit inputs — two operands (a, b) and a carry-in (cin) — and produces:

• sum (1 bit)
• cout (carry-out, 1 bit)

You’ll design the full adder and verify it with all input combinations.

Explanation (How it works)

Think of column-wise binary addition:

• The sum bit is the XOR of all three inputs.
• The carry-out goes high when at least two of the inputs are 1.

Two common realizations:

1. Equation form

• sum = a ^ b ^ cin
• cout = (a & b) | (cin & (a ^ b))

1. Two half-adders + OR

• Half-Adder1: s1 = a ^ b, c1 = a & b
• Half-Adder2: sum = s1 ^ cin, c2 = s1 & cin
• cout = c1 | c2

Requirements

1. Create a Verilog module named full_adder with:
   • Inputs: a, b, cin
   • Outputs: sum, cout
2. Implement using either the equation form or two half-adders method.
3. Write a testbench module to verify the design:
   • Apply all 8 input combinations for {a,b,cin} from 000 to 111.
   • Check sum and cout against the truth table (use waveforms; no $display needed).

Expected Truth Table

Test Plan (What to do)

1. Simulate the testbench and inspect waveforms for a, b, cin, sum, cout.
2. Verify that sum toggles as XOR of all three, and cout goes high when ≥2 inputs are 1.
3. (Optional) Add small delays between vector changes so edges are visible in the VCD.

Common Pitfalls

• Mixing up cout equation: ensure cout = (a & b) | (cin & (a ^ b)).
• Not testing all 8 combinations.
• Forgetting to name the testbench module exactly testbench.

Extension (Challenge)

• Chain four full_adder modules to build a 4-bit ripple-carry adder with cin and cout.
• Use our editor and try it out there

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